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Integrated Circuit Systems, Inc.
ICS97ULPA877A
1.8V Low-Power Wide-Range Frequency Clock Driver
Recommended Application: * DDR2 Memory Modules / Zero Delay Board Fan Out * Provides complete DDR DIMM logic solution with ICSSSTU32864/SSTUF32864/SSTUF32866/ SSTUA32864/SSTUA32866/SSTUA32S868/ SSTUA32S865/SSTUA32S869 Product Description/Features: * Low skew, low jitter PLL clock driver * 1 to 10 differential clock distribution (SSTL_18) * Feedback pins for input to output synchronization * Spread Spectrum tolerant inputs * Auto PD when input signal is at a certain logic state Switching Characteristics: * Period jitter: 40ps (DDR2-400/533) 30ps (DDR2-667/800) * Half-period jitter: 60ps (DDR2-400/533) 50ps (DDR2-667/800) * OUTPUT - OUTPUT skew: 40ps (DDR2-400/533) 30ps (DDR2-667/800) * CYCLE - CYCLE jitter 40ps
Pin Configuration
1 A B C D E F G H J K 2 3 4 5 6
52-Ball BGA
Top View
A B C D E F G H J K 1 CLKT1 CLKC1 CLKC2 CLKT2 CLK_INT CLK_INC AGND AVDD CLKT3 CLKC3 2 CLKT0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND CLKC4 3 CLKC0 GND NB VDDQ NB NB VDDQ NB GND CLKT4 4 CLKC5 GND NB VDDQ NB NB VDDQ NB GND CLKT9 5 CLKT5 GND GND OS VDDQ OE VDDQ GND GND CLKC9 6 CLKT6 CLKC6 CLKC7 CLKT7 FB_INT FB_INC FB_OUTC FB_OUTT CLKT8 CLKC8
Block Diagram
OE OS AVDD Powerdown Control and Test Logic LD* or OE LD*, OS or OE CLKC0 CLKT1 CLKC1 CLKT2 LD* PLL bypass CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5 CLK_INT CLK_INC 10K-100k PLL GND FB_INT FB_INC * The Logic Detect (LD) powers down the device when a logic low is applied to both CLK_INT and CLK_INC. CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 FB_OUTT FB_OUTC
40
VDDQ CLKC2 CLKT2 CLK_INT CLK_INC VDDQ AGND AVDD VDDQ GND
CLKC1 CLKT1 CLKT0 CLKC0 VDDQ CLKC5 CLKT5 CLKT6 CLKC6 VDDQ
31
CLKT0
1
30
ICS97ULPA877A
10
21 11 20
CLKC7 CLKT7 VDDQ FB_INT FB_INC FB_OUTC FB_OUTT VDDQ OE OS
1088B--01/18/06
CLKT3 CLKC3 CLKC4 CLKT4 VDDQ CLKT9 CLKC9 CLKC8 CLKT8 VDDQ
40-Pin MLF
ICS97ULPA877A
Pin Descriptions
Te r m i n a l Name AGND AVDD CLK_INT CLK_INC FB_INT FB_INC FB_OUTT FB_OUTC OE OS GND VDDQ CLKT[0:9] CLKC[0:9] NB Analog Ground A n a l o g p ow e r Clock input with a (10K-100K Ohm) pulldown resistor Complentar y clock input with a (10K-100K Ohm) pulldown resistor Feedback clock input Complementary feedback clock input Feedback clock output Complementary feedback clock output Output Enable (Asynchronous) Output Select (tied to GND or VDDQ) Ground Logic and output power Clock outputs Complementary clock outputs No ball Description Electrical Characteristics Ground 1.8 V nominal Differential input Differential input Differential input Differential input Differential output Differential output LVCMOS input LVCMOS input Ground 1.8V nominal Differential outputs Differential outputs
The PLL clock buffer, ICS97ULPA877A, is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF. ICS97ULPA877A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or VDDQ. When OS is high, OE will function as described above. When OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC) within the specified stabilization time tSTAB. The PLL in ICS97ULPA877A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ICS97ULPA877A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. ICS97ULPA877A is characterized for operation from 0C to 70C.
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ICS97ULPA877A
Function Table
Inputs AVDD GND GND GND GND 1.8V(nom) 1.8V(nom) 1.8V(nom) 1.8V(nom) 1.8V(nom) 1.8V(nom) OE H H L L L L H H X X OS X X H L H L X X X X CLK_INT L H L H L H L H L H CLK_INT H L H L H L H L L H CLKT L H *L(Z) *L(Z), CLKT7 active *L(Z) *L(Z), CLKT7 active L H *L(Z) CLKC H L *L(Z) *L(Z), CLKC7 active *L(Z) *L(Z), CLKC7 active H L *L(Z) Outputs PLL FB_OUTT L H L H L H FB_OUTC H L H L Bypassed/Off Bypassed/Off Bypassed/Off Bypassed/Off
H L
On On
L H *L(Z) Reser ved
H L *L(Z)
On On Off
*L(Z) means the outputs are disabled to a low stated meeting the IODL limit.
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ICS97ULPA877A
Absolute Maximum Ratings
Supply Voltage (VDDQ & AVDD) . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 2.5V GND - 0.5V to VDDQ + 0.5V 0C to +70C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) SYMBOL MIN TYP PARAMETER CONDITIONS Input High Current IIH VI = VDDQ or GND (CLK_INT, CLK_INC) Input Low Current (OE, IIL VI = VDDQ or GND OS, FB_INT, FB_INC) Output Disabled Low OE = L, VODL = 100mV IODL 100 Current IDD1.8 CL = 0pf @ 410MHz Operating Supply Current CL = 0pf IDDLD VDDQ = 1.7V Iin = -18mA VIK Input Clamp Voltage VDDQ - 0.2 IOH = -100 A VOH High-level output voltage IOH = -9 mA 1.1 1.45 IOL=100 A 0.25 VOL Low-level output voltage IOL=9 mA 1 CIN VI = GND or VDDQ 2 Input Capacitance 1 COUT 2 VOUT = GND or VDDQ Output Capacitance
1
MAX 250 10
UNITS A A A
300 500 -1.2
0.10 0.6 3 3
mA A V V V V V pF pF
Guaranteed by design, not 100% tested in production.
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ICS97ULPA877A
Recommended Operating Condition (see note1)
TA = -40C - 85C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER Supply Voltage Low level input voltage SYMBOL V DDQ, AVDD V IL CONDITIONS MIN 1.7 TYP 1.8 MAX 1.9 0.35 x V DDQ 0.35 x V DDQ UNITS V V V V V V DDQ + 0.3 V DDQ + 0.4 V DDQ + 0.4 V DDQ/2 + 0.10 V V V V V mA mA C
High level input voltage DC input signal voltage (note 2) Differential input signal voltage (note 3) Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) High level output current Low level output current Operating free-air temperature
VIH VIN
CLK_INT, CLK_INC, FB_INC, FB_INT OE, OS CLK_INT, CLK_INC, FB_INC, 0.65 x VDDQ FB_INT OE, OS 0.65 x VDDQ -0.3 DC - CLK_INT, CLK_INC, FB_INC, FB_INT AC - CLK_INT, CLK_INC, FB_INC, FB_INT 0.3 0.6 VDDQ/2 - 0.10
VID
VOX VIX IOH IOL TA
VDDQ/2 - 0.15 VDD/2 V DDQ2 + 0.15 -9 9 -40 85
Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signal must be crossing.
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ICS97ULPA877A
Timing Requirements
TA = 0 - 70C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN MAX Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization freqop freqApp dtin TSTAB 1.8V+0.1V @ 25C 1.8V+0.1V @ 25C 95 160 40 410 410 60 15 UNITS MHz MHz % s
NOTE: The PLL must be able to handle spread spectrum induced skew. NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters. NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal, within the value specificied by the Static Phase Offset (t(AE ), after power-up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle.
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ICS97ULPA877A
Switching Characteristics1
TA = 0 - 70C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER CONDITION (MHz) SYMBOL ten Output enable time OE to any output 160 to 410 tdis OE to any output Output disable time 160 to 270 tjit (per) Period jitter 271 to 410 160 to 270 tjit(hper) Half-period jitter 271 to 410 Input Clock Input slew rate SLr1(i) Output Enable (OE), (OS) Output clock slew rate 160 to 410 SLr1(o) tjit(cc+) Cycle-to-cycle period jitter tjit(cc-) 160 to 270 t(O)dyn Dynamic Phase Offset 271 to 410 2 Static Phase Offset 271 to 410 tSPO (su) t jit (per) + t (O)dyn + t skew(o) t(O)dyn + tskew(o) t (h) 160 to 270 tskew Output to Output Skew 271 to 410 SSC modulation frequency SSC clock input frequency deviation PLL Loop bandwidth (-3 dB from unity gain) MIN TYP 4.73 5.82 MAX 8 8 40 30 60 50 4 3 40 -40 50 20 50 80 60 40 30 33 -0.50 UNITS ns ns ps ps ps ps v/ns v/ns v/ns ps ps ps ps ps ps ps ps ps kHz % MHz
-40 -30 -60 -50 1 0.5 1.5 0 0 -50 -20 -50
2.5 2.5
0
30.00 0.00 2.0
Notes: 1. Switching characteristics guaranteed for application frequency range. 2. Static phase offset shifted by design.
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ICS97ULPA877A
Parameter Measurement Information VDD V(CLKC)
V(CLKC) ICS97ULPA877A GND Figure 1. IBIS Model Output Load VDD/2 ICS97ULPA877A Z = 60 Z = 2.97" Z = 120 Z = 60 Z = 2.97" C = 10 pF GND -VDD/2 Figure 2. Output Load Test Circuit
R = 1M V(TT) C = 1 pF R = 1M V(TT) C = 1 pF
C = 10 pF - GND R = 10 Z = 50
SCOPE
R = 10
Z = 50
Note: VTT = GND
YX, FB_OUTC YX, FB_OUTT tc(n) tc(n+1) tjit(cc) = tc(n) tc(n+1) Figure 3. Cycle-to-Cycle Jitter
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ICS97ULPA877A
Parameter Measurement Information CLK_INC CLK_INT
FB_INC FB_INT
t( ) n
n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset
t ( ) n+1
YX# YX
YX, FB_OUTC YX, FB_OUTT t(skew) Figure 5. Output Skew
YX, FB_OUTC YX, FB_OUTT YX, FB_OUTC YX, FB_OUTT
tC(n)
1 fO t(jit_per) = tc(n) - 1 fO Figure 6. Period Jitter
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ICS97ULPA877A
Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT
t jit(hper_n) 1 fo t jit(hper_n+1)
tjit(hper) = t jit(hper_n)
-
1 2xfO
Figure 7. Half-Period Jitter
80%
80% VID, VOD
Clock Inputs and Outputs
20% tslr tslf
20%
Figure 8. Input and Output Slew Rates
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ICS97ULPA877A
CK CK FBIN FBIN
t(
SSC OFF SSC ON
)
SSC ON
t(
SSC OFF
)
t(
)dyn
t(
)dyn
t(
)dyn
t(
)dyn
Figure 9. Dynamic Phase Offset
50% VDDQ OE t en 50% VDDQ Y/ Y Y Y
OE
50% VDDQ t dis 50 % VDDQ Y
Figure 10. Time delay between OE and Clock Output (Y, Y)
Y
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ICS97ULPA877A
Figure 11. AVDD Filtering
- Place the 2200pF capacitor close to the PLL. - Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one GND via (farthest from PLL). - Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz).
1088B--01/18/06
12
ICS97ULPA877A
C Seating Plane A1 T b REF Numeric Designations for Horizontal Grid 4321 A B C D
D
Alpha Designations for Vertical Grid (Letters I, O, Q & S not used)
d TYP D1 - e - TYP TOP VIEW
E
h TYP 0.12 C
c REF E1
- e - TYP
ALL DIMENSIONS IN MILLIMETERS D 7.00 Bsc E 4.50 Bsc T Min/Max 0.86/1.00 e 0.65 Bsc ----- BALL GRID ----HORIZ VERT 6 10 Max. TOTAL 60 d Min/Max 0.25/0.45 h Min/Max 0.15/0.21 D1 5.85 Bsc E1 3.25 Bsc REF. DIMENSIONS b c 0.575 0.625 **
Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEDEC Publication 95, 10-0055 MO-205*, MO-225**
Ordering Information
ICS97ULPA877AH(LF)-T
Example:
ICS XXXX y H LF- T
Designation for tape and reel packaging RoHS Compliant (Optional) Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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ICS97ULPA877A
Seating Plane Index Area N 1 2 E Top View Anvil Singulation or Sawn Singulation E2
E2 2
(Ref.)
(N D -1)x e
A1 A3 L
(Ref.)
ND & NE Even N 1 2 (NE -1)x e
(Ref.) (Typ.) e 2 If N & N D E
are Even
b A
(Ref.)
e D2 2 D2
D
ND & NE Odd C
Thermal Base
0.08
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE
ALL D IMENSIONS IN MILLIMETERS
N ND NE D x E BASIC D2 M IN. / MAX. E2 M IN. / MAX. L MIN. / MAX.
40 10 10 6.00 x 6.00 2.75 / 3.05 2.75 / 3.05 0.30 / 0.50
SY MBOL A A1 A3 b e
MIN. M AX. 0.80 1.00 0 0.05 0.25 Reference 0.18 0.30 0.50 BASIC
Source R eference: MLF2TM SE
10-0053
Ordering Information
ICS97ULPA877AK(LF)-T
Example:
ICS XXXX y K LF- T
Designation for tape and reel packaging RoHS Compliant (Optional) Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
1088B--01/18/06
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ICS97ULPA877A
Revision History
Rev. B Issue Date Description 1/18/2006 Updated Package dimensions. Page # 13
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15

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